1. Field of the Invention
This invention relates to a semiconductor integrated circuit, for example, and more particularly to a semiconductor integrated circuit having test circuits called a boundary scan test circuit for evaluating the characteristic thereof.
2. Description of the Related Art
As is well known in the art, in order to make an in-circuit test of a semiconductor integrated circuit device mounted on a printed circuit board, conventionally, a probe connected to the tester is brought into contact with the external terminal of the semiconductor integrated circuit, a signal necessary for the test is input via the probe and an output signal for the input signal is received. However, in the present semiconductor integrated circuit device, the pitch of the external terminals becomes extremely small with further development of the packaging technique. Particularly, it becomes difficult to correctly set the probe in contact with only one of the pins of the semiconductor chip on the surface mounting type package. For this reason, various test methods have been developed. As one of the test methods, the boundary scan test has been provided.
FIG. 5 shows a semiconductor integrated circuit device having a conventional boundary scan test circuit contained therein. In a semiconductor substrate 11, an internal circuit 12 such as a microprocessor is formed, for example. A plurality of test circuits 13.sub.1 to 13.sub.n called boundary scan cells are arranged around the internal circuit 12. The test circuits 13.sub.1 to 13.sub.i are respectively connected to input pads 14.sub.1 to 14.sub.i and the test circuits 13.sub.j to 13.sub.n are respectively connected to output pads 14.sub.j to 14.sub.n. In the normal operation mode, the test circuits 13.sub.1 to 13.sub.i supply signals supplied from the input pads 14.sub.1 to 14.sub.i to the internal circuit 12 and the test circuits 13.sub.j to 13.sub.n output signals output from the internal circuit 12 to the output pads 14.sub.j to 14.sub.n. The test circuits 13.sub.1 to 13.sub.n are serially connected via a scan path 15 in the boundary scan test mode so as to function as a so-called shift register. One end of the shift register is connected to a test data input pad 16 and the other end thereof is connected to an output pad 17 for outputting test data.
FIG. 6 shows the construction of the test circuit 13.sub.1. The data inputting test circuits 13.sub.1 to 13.sub.i have the same construction. The input pad 14.sub.1 is connected to one input terminal of a multiplexer acting as selection means via an input buffer 21. The output terminal of the multiplexer 22 is connected to the internal circuit 12 and to one input terminal of a multiplexer 23. The other input terminal of the multiplexer 23 is connected to the test data input pad 16 via the scan path 15. The multiplexer 23 is controlled by a shift mode changing signal SM and the output terminal of the multiplexer 23 is connected to the input terminal of a flip-flop circuit 24. The clock signal input terminal of the flip-flop circuit 24 is supplied with a shift clock signal CKDR for shifting test data in the test mode, and the output terminal thereof is connected to a next stage test circuit (not shown) via the scan path 15 and to the input terminal of a flip-flop circuit 25. The clock signal input terminal of the flip-flop circuit 25 is supplied with an update signal UDS used as a timing signal for supplying test data held in the flip-flop circuit 24 to the internal circuit 12 in the test mode and the output terminal thereof is connected to the other input terminal of the multiplexer 22. The multiplexer 22 is supplied with a switching signal TRU, and the multiplexer 22 selects an output signal of the input buffer 21 in the normal operation mode and selects an output signal of the flip-flop circuit 25 in the boundary scan test mode according to the switching signal TRU.
With the above construction, test data supplied from the test data input pad 16 is serially set into the flip-flop circuits 24 of the test circuits 13.sub.1 to 13.sub.i in response to the shift clock signal CKDR. Test data set in each of the test circuits 13.sub.1 to 13.sub.i is transferred to the internal circuit 12 in response to the update signal UDS and signals output from the internal circuit 12 are transferred to the test circuits 13.sub.j to 13.sub.n.
In the conventional boundary scan test, test data is simultaneously supplied to the internal circuit 12 at a preset timing defined by the update signal UDS with the test data set in the test circuits 13.sub.1 to 13.sub.i. It is necessary to input the test data items to the respective input pins (not shown) of the internal circuit 12 at preset timings. For example, in a case where test data items of two steps shown in FIG. 8A are supplied to input pins P1 to P4 (not shown) of the internal circuit 12 at such preset timings as shown in FIG. 7, it is necessary to convert data shown in FIG. 8A to data shown in FIG. 8B before transferring the data. That is, in the boundary scan test, data cannot be input to a plurality of test circuits 13.sub.1 to 13.sub.i in parallel, but is serially input. For this reason, in order to supply test data set in the test circuits 13.sub.1 to 13.sub.i at timings shown in FIG. 7 by the update signal UDS, it is necessary to previously convert data shown in FIG. 8A to data shown in FIG. 8B according to the timings shown in FIG. 7. That is, data shown in FIG. 8B divides data shown in FIG. 8A into a plurality of steps at level-shifting points of the waveforms shown in FIG. 7. In the actual test, the operation of setting the thus converted test data into each of the test circuits for each step, and then, supplying each test data set by the update test signal to the internal circuit is repeatedly effected.
Thus, in the conventional boundary scan test circuit, test data items set in the respective test circuits are simultaneously supplied to the internal circuit. For this reason, when parallel test data whose input timing is previously defined is converted into serial test data, the test data must be divided into a plurality of steps according to the input timing. Therefore, the number of steps of the test data is increased and time for the test becomes longer.